In certain applications for which memory is required, new data to be written to the cells of a memory array are available before existing data is read from those cells. For example, when buffering packets of data during asynchronous transfer mode (ATM) switching, new data packets are presented to memory at the same time as existing packets can be read from memory. In such applications, it would be desirable to read the existing data and write the new data to the memory cells within a single memory cycle, so as to achieve maximum performance for a selected clock speed.
Conventional memory circuits, however, provide less than optimum performance. Conventional memory circuits require at least two memory cycles to perform both the read and write functions--existing data are read from memory during a first memory cycle, and new data are written to the memory in a subsequent memory cycle. To increase the operating speed of a conventional memory, a higher clock speed is required. Such a faster memory would consume more power and provide smaller storage capacity, and typically may necessitate fabricating the memory using a more complex and expensive technology.